# Counter Circuits: Definition, Types & Design

Shadi has a Ph.D. in Computer Science and more than 20 years experience in industry and higher education.

In this lesson, we will take a look at a particular type of sequential circuits called counters. We will then distinguish between two different ways of designing counters that lead to two different kinds of counters. synchronous and asynchronous counters. While synchronous counters are easier to design, asynchronous counters are more interesting in terms of power consumption.

## Introduction

You might think of a counter as a circuit that counts events, for example people entering a room. However, in the universe of digital design and Boolean circuits, a binary digital counter is a sequential circuit of which the transfer among states is fixed, regardless if the states are arithmetically ordered or not. For example, the circuit that constantly moves through the following same order of state transfers 1, 0, 2, 5, 7 then gets back to 1 is called a counter (it is often accepted that a counter restarts when it reaches the final number). Of course, the circuit that moves through the states 0, 1, 2, 3, 4, 5, 6 (then gets back to 0) is also a counter.

## Types of Counters

### Synchronous Counters

A synchronous counter is a counter that all its FFs (FFs is an abbreviation of flip-flops) are clocked by the same signal. Let us design a counter that counts the following order 0,1,3,2,7,4 using JK-FFs. Notice that for better time performance, we often use Master/Slave JK-FFs (we will refer to this kind of FFs by MSJK-FFs). In order to design this counter, we start by determining the number of the required FFs. Because the highest counted number is 7 and it can be binary coded using 3 bits, we will use three FFs to design the counter. We will name the FFs A, B and C and we will assume that A is the least significant bit. This will give the circuit in Figure 1.

Now, we need to determine the values of J and K for each FF. In order to do this, we need to write the counter's state table. The state table will be the following.

Decimal C B A C+ B+ A+ JA KA JB KB JC KC
0 0 0 0 0 0 1
1 0 0 1 0 1 1
3 0 1 1 0 1 0
2 0 1 0 1 1 1
7 1 1 1 1 0 0
4 1 0 0 0 0 0

In the previous table, A+, B+ and C+ represent the next states of A, B and C respectively. In order to complete this table, we will use the following JK state transfer table.

Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Accordingly, the counter's state table will be completed as follows.

Decimal C B A C B A JA KA JB KB JC KC
0 0 0 0 0 0 1 1 X 0 X 0 X
1 0 0 1 0 1 1 X 0 1 X 0 X
3 0 1 1 0 1 0 X 1 X 0 0 X
2 0 1 0 1 1 1 X 0 X 0 1 x
7 1 1 1 1 0 0 X 1 X 1 X 0
4 1 0 0 0 0 0 0 X 0 X X 1

We can simplify JA, KA, JB, KB, JC and KC as functions to A, B and C. Use any method you like to do the simplification and you should get: (The output is Q. In the following Q', is equivalent to NOT Q):

• JA=C'
• KA=AB
• JB=A
• KB=C
• JC=BA'
• KC= B'

Now, we can complete the circuit of the counter by connecting the Js and Ks of the FFs as given above, getting the counter shown in Figure 2.

### Asynchronous Counters

In synchronous counters, all FFs are clocked using the same signal. This is not the case in asynchronous counters. In asynchronous counters, we try to clock each FF from one of the FFs that precede in significance. In other words, if we are using 3 FFs: C, B and A, and C is the most significant bit, then we will try to clock B from, if not possible, then it will be clocked from the same signal clocking A (Least significant bit FF is always clocked from the counted event signal). For C, we will start by trying to clock it from B, if not possible, we will try to use A to clock it and if this is not possible, we will clock it from the same signal as A. Let us look at an example to understand this. Let us design an asynchronous counter that counts 0, 1, 2, 3, 4, 5, 6 using MSJK-FFs. The first step in the design process for this example is to find the clock sources of each FF. In order to do this, we will check if there is a triggering edge that matches each state transfer of the counter. Let us look at the output sequence in Figure 3 that shows the states transfers of B. From the figure we can see that the transfers marked by red match falling edges (the blue arrow show a transfer from 1 to 0, which represents a falling edge). However, the last transfer, marked by green, does not match an edge (A keeps its 0 state). This means that it is not possible to clock B from A and it should be clicked from the same signal clocking A.

Let us now look at clocking C in Figure 4. In this Figure, we can see that all state transfers in C match a falling edge in B. This means that C can be clocked from B.

This leads to the circuit in Figure 5.

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