How the Number Operands of an Instruction Set Affects the Assembly Language

Instructor: Shadi Aljendi

Shadi has a Ph.D. in Computer Science and more than 20 years experience in industry and higher education.

When you design the instruction set of a processor, you need to make important decisions. Some decisions may make your hardware design complex, but they will simplify the ability to write programs for it. Other decisions may make for a simple hardware design, but create complex programming. In this lesson, we will take a look at the effect the number of machine instruction operands has on the complexity of an assembly program. Updated: 10/29/2019

Introduction

Designing a microprocessor is a complex process that involves making a number of decisions that might often lead to contradictory results. For example, if you decide to make programming easy for the user, you may find yourself having to design very complex hardware. In this lesson, we will look at an example of this by studying the effect of machine instruction complexity on an assembly language program.

The Different Structures of Machine Instructions

A 2-operand machine instruction must include (implicitly or explicitly) the following parts:

  • The operation
  • Source 1 which represents the first operand
  • Source 2 which represents the second operand
  • The destination which is the register or the memory address that will store the result of the instruction

Each one of these fields must be coded using a certain number of bits. The number of required bits is determined by the number of possibilities in each field. The number of bits for the operation field is determined by the number of native processor operations. The number of bits for each of the remaining fields is determined by the operation's addressing space.

Depending on the architecture, one of the addressing fields could be implicit. Usually, when the destination is implicit, it will be in one of the sources (often source 1). In some architectures, both one of the sources and the destination could be implicit. In this case, the implicit source and the destination would be a particular address or register. Often, this register is called the Accumulator (Acc). When the sources and the destination are implicit, we get a stack processor.

Practical Examples

In order to understand the effect of the number of operands of an instruction, 4 processors of different architecture are introduced below.

Processor 1

Processor 1 is a 3-address processor that is capable of executing the following instructions:

Instruction Explanation
ADD A, B, C Add the contents of B to the contents of C and store the result in A
SUB A, B, C Subtract the contents of C from the contents of B and store the result in A
MUL A, B, C Multiply the contents of B by the contents of C and store the result in A
DIV A, B, C Divide the contents of B by the contents of C and store the result in A

A, B and C are either processor registers or memory locations. Supposing that each field in the instruction set can be coded using 4 bits, all the previous instructions can be coded into 16 bits. Because this processor defines a destination for its operations, the processor does not need a MOV instruction.

Processor 2

Processor 2 is a 2-address processor that is capable of executing the following instructions:

Instruction Explanation
ADD A, B Add the contents of A to the contenst of B and store the result in A
SUB A, B Subtract the contents of B from the contents of A and store the result in A
MUL A, B Multiply the contents of A by the contents of B and store the result in A
DIV A, B Divide the contents of A by the contents of B and store the result in A
MOV A, B Copy the contents of B into A

Using the same assumption as for Processor 1, all the previous instructions can be coded into 12 bits.

Processor 3

Processor 3 is a 1-address processor that is capable of executing the following instructions:

Instruction Explanation
ADD B Add the contents of B to the contents of the accumulator Acc and store the result in Acc
SUB B Subtract the contents of B from the contents of the accumulator Acc and store the result in Acc
MUL B Multiply the contents of B by the contents of the accumulator Acc and store the result in Acc
DIV B Divide the contents of the accumulator Acc by the contents of B and store the result in Acc
LD B Copy the contents of B in the accumulator Acc
STR B Copy the contents of the accumulator Acc to B

Using the same assumption as for Processor 1, all the previous instructions can be coded into 8bits.

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